As the channel length (L) is reduced or as the channel width Wp or Wn) is increased, the influence of a resistance at the gate electrode of a MOSFET becomes unignorable and switching characteristics deteriorate. Consequently, an arrangement has been made to reduce the influence of the gate resistance by supplying an input signal IN from both ends of the gate electrodes 502, 504 of the MOSFET inverter 500 as shown in FIG. 5.
In a circuit for supplying an input signal from both end sides of the gate electrode of such a MOSFET using two-layer wiring, the wire should be arranged in such a manner as to bypass the source 506, 508 and drain 570, 572 diffusion layers in substrate 514 as shown by a dotted line of FIG. 5 in order to prevent it from crossing a signal line for taking an output signal out of the MOSFET and wires for use in supplying power supply voltage Vee and Vss. The problem in this case is that the layout area tends to increase.
It is an object of the present invention to provide a semiconductor integrated circuit designed to accomplish high-speed operation and increased integration by arranging a metal wiring layer associated with the gate electrode of a MOSFET in such a manner as to avoid an increase of the layout area.